Present and future high-reliability (that is, space) missions require significant increases in on-board signal processing. Presently, generated data is not transmitted via downlink channels in a reasonable time. As users of the generated data demand faster access, increasingly more data reduction or feature extraction processing is performed directly on the high-reliability vehicle (for example, spacecraft) involved. Increasing processing power on the high-reliability vehicle provides an opportunity to narrow the bandwidth for the generated data and/or increase the number of independent user channels.
In signal processing applications, traditional instruction-based processor approaches are unable to compete with million-gate, field-programmable gate array (FPGA)-based processing architectures. Systems with multiple FPGA-based processors are required to meet computing needs for Space Based Radar (SBR), next-generation adaptive beam forming, and adaptive modulation space-based communication programs. As the name implies, an FPGA-based system is easily reconfigured to meet new requirements. FPGA-based reconfigurable processing architectures are also re-useable and able to support multiple space-based communication programs with relatively simple changes to their unique data interfaces.
Existing commercial-off-the-shelf (COTS), synchronous read-only memory (SRAM)-based processing elements are sensitive to radiation-induced upsets. Consequently, traditional COTS-based reconfigurable systems are unreliable in high-radiation environments. Furthermore, existing diagnostic approaches for detecting and mitigating susceptibilities to one or more single event upsets (SEUs), single event functional interrupts (SEFIs) and single event transients (SETs) have several disadvantages, particularly with respect to partial reconfiguration. Partial reconfiguration involves replacing (restoring) dynamic memory register contents with new (existing) processing configurations while leaving static memory register contents intact. Current methods of partial reconfiguration remove radiation effects in dynamic memory portions of the processing system while (potentially) leaving static memory portions with accumulated radiation over a significant time period.